1. Field of the Invention
Embodiments of the invention relate to non-volatile memory devices. More particularly, embodiments of the invention relate to flash memory devices and a related erase operation.
This application claims priority under 35 U.S.C § 119 to Korean Patent Application 2005-131876 filed on Dec. 28, 2005, the subject matter of which is hereby incorporated by reference.
2. Discussion of Related Art
Semiconductor memory devices may be categorized as volatile or non-volatile in relation to the nature of their data storage capabilities. In general, volatile memory devices allow high speed read/write operations, but lose stored data when power is interrupted. In contrast, non-volatile memory devices retain stored data even when power is interrupted. As a result, non-volatile memory is typically used for applications requiring the retention of stored data regardless of power state.
Within the broad class of non-volatile memory devices, so-called “flash” electrically erasable programmable read-only memory (EEPROM) devices (hereafter, “flash memory”) enjoy several fabrication and performance advantages. For example, flash memory may be easily incorporated at low cost into host devices requiring mass storage capability, because their integration densities are very high relative to conventional EEPROMs. Flash memory is conventionally provided in two primary types—NAND flash memory and NOR flash memory. Each has its own benefits over the other. For example, NOR flash memory provides relatively high speed read/programming operations.
FIG. 1 is a cross-sectional view of a conventional flash memory cell 10. FIG. 2 is a related graph illustrating the distribution of threshold voltages for an ON state and an OFF state of memory cell 10 shown in FIG. 1.
As illustrated in FIG. 1, flash memory cell 10 includes a source region 12 and a drain region 13 formed in a P-type semiconductor substrate 11 (e.g., a bulk semiconductor substrate). A channel region 15 is formed between source region 12 and drain region 13. A thin insulator 14 and a floating gate 16 are disposed over the channel region 15. The thin (first) insulator 14 having a thickness of about 100 angstroms separates a floating gate 16 from channel region 15. A second insulator 17 separates floating gate 16 from an overlaying control gate 18. Control gate 18 is commonly connected with a wordline.
A NOR flash memory cell is programmed by applying a ground voltage (0 volt) to source region 12 and semiconductor substrate 11, a high voltage (about 10 volts) to control gate 18, and an intermediate voltage (5 volts) suitable for generating hot electrons in drain region 13. Under the influence of this programming scheme, negative charge will be accumulated on floating gate 16. As a result, floating gate 16 will develop a negative voltage. This being the case, a corresponding threshold voltage for flash memory cell 10 will rise during a following read operation as the negative charge is dissipated from floating gate 16.
The read operation may be conducted by applying an intermediate voltage (about 5 volts) to control gate 18 and a ground voltage to source region 13. Under the influence of these voltages, channel region 15 of a previously programmed memory cell (i.e., one programmed such that its threshold voltage rises when read) will not become conductive. That is, memory cell 10 is placed in an OFF state and a threshold voltage of the memory cell is distributed to within a range between 7 volts to 9 volts, as illustrated in FIG. 2.
Flash memory cells are typically arranged in groups generally referred to as sectors. The flash memory cells in a given sector may be simultaneously erased by the well known F-N tunneling scheme in which a high negative voltage (about −10 volt) is applied to control gate 18 and a positive voltage (6-9 volts) suitable for generating the F-N tunneling effect is applied to semiconductor substrate 11. Under the influence of these voltages, source region 12 and drain region 13 are maintained in floating state. The resulting bias condition, produces a strong electric field (about 6-7 MV/cm) between control gate 18 and semiconductor substrate 11, thereby generating the F-N tunneling effect. Due to this effect, negative charge accumulates on floating gate 16 as it migrates from source region 12 through thin first insulator 15. Thus, the threshold voltage of flash memory cell 10 drops during the read operation.
Various erasing operations for flash memory devices are disclosed, for examples, in U.S. Pat. Nos. 5,781,477; 5,132,955; 5,220,533; 5,513,193; and 5,805,501, the subject matter of which is hereby incorporated by reference.
Summarizing certain aspects of these convention erase operations, the threshold voltage of an erased flash memory cell is typically distributed within a range of between 1 to 3 volts. However, when memory cells of a sector are simultaneously erased, the threshold voltage of one or more of the individual flash memory cell(s) may drop below 1 volt. In such circumstances, the flash memory cell having a voltage of 1 volt or less is said to be “overerased.” The corresponding threshold voltage of an overerased flash memory cell may be corrected through an erase repair operation adapted to shift it back into a target threshold voltage range (e.g., 1-3 volts) corresponding to an ON state for the flash memory cell. Programming operations adapted to correct the threshold voltage of an overerased flash memory cell following an erase operation are referred to as post-programming operations.
FIG. 3 illustrates one example of a conventional erase operation adapted for use with a NOR flash memory device. Characteristic threshold voltage distributions are shown in relation to the constituent steps of the convention erase operation. Thus, the conventional erase operation generally includes a pre-programming operation S20, a main erasing operation S30, and a post-programming operation S40.
Pre-programming operation S20 may be conducted under the same bias conditions described above in relation to the normal programming operation. Pre-programming operation S20 may include a program operation and a program verify operation—both conventionally understood. Until all memory cells in a particular sector selected during pre-programming operation S20 are placed in properly programmed state, the program operation and the program verify operation may be repeated. As a result, the threshold voltages of the programmed memory cells shift to about 7 volts or higher (i.e., a threshold voltage corresponding to an OFF state for the flash memory cell).
Main erasing operation S30 allows all memory cells in the selected sector to be placed in an ON memory cell state. Main erasing operation S30 may include an erase operation and an erase verify operation. The erase operation may be conducted under the same bias condition described above in relation to the programming operation. Until all memory cells in a sector selected during the main erasing operation S30 are placed in an erase state, the erase operation and the erase verify operation may be repeated.
However, the individual memory cells in a selected sector will have different erase speeds. Accordingly, although pre-programming operation S20 has been uniformly applied to all of the memory cells in the sector, there may nonetheless be memory cells overerased by main erasing operation S30. In order to correct the threshold voltage of such overerased memory cells, post-programming operation S40 is performed.
Post-programming operation S40 is performed by grounding substrate 11 and source 12 of an overerased memory cell, connecting control gate 18 of the overerased memory cell to a voltage (e.g., 3 volts) lower than the programming voltage (e.g., 10 volts), and connecting drain 13 of the overerased memory cell to an intermediate voltage (about 5-6 volts). As a result of this voltage bias condition, negative charge is again accumulated on floating gate 16, albeit the quantity of negative charge accumulated is less than that accumulated during the programming operation. Post-programming operation S40 may, thus, be conducted under conditions highly analogous to pre-programming operation S20. As a result of post-programming operation S40, the threshold voltage of an overerased flash memory cell may be shifted to within a target threshold voltage range (e.g., 1-3 volts) corresponding to an ON state for the flash memory cell.
As one may understand from the foregoing summary of conventional erase operations and from a more detailed review of the incorporated references, an erase operation for a NOR flash memory device is a very complex procedure. Memory cells of a conventional NOR flash memory device are erased on a sector by sector basis. For this reason, individual erase operations for respective sectors must be conducted sequentially. Namely, after an erase operation is performed on one sector of memory cells, including all of the steps described in relation to the flowchart of FIG. 3, the erase operation must be separately performed for the next sector of memory cells. Thus, the total time required for a global erase operation in a NOR flash memory device is equal to the multiple of the time required to perform one sector erase operation times the number of sectors being erased. As NOR flash memory devices increase in size, so too does the number of sectors. As the number of sectors increase, the time required to perform a global erase operation also increases.